Spec

• The HC273 is a positive logic edge-triggered D flip-flop with an active clear (CLR) input.
• Data (D) input information that meets the setup time requirement is transferred to the Q output at the rising edge of the clock (CLK) pulse. Clock triggers occur at specific voltage levels and are not directly related to the transition time of the positive pulse. If the CLK is at high or low logical level, the D input does not affect the output.
• Specifications and Operating Voltage Range: 2V~6V
• Can drive up to 10 LSTTL loads
• Three-state output can drive busline/buffer memory address registers
• ICC:80μA(max)
• tpd:12ns
• +/-4mA output drive at 5V
• Input current: 1 μA (max)
• *For MIL-PRF-38535 compliant products, all parameters are tested unless otherwise specified.
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